1. Field of the Invention
The invention generally relates to semiconductor memory devices, and more particularly to an improved circuit for detecting the existence of a defective memory cell in a semiconductor memory device in a short time. The present invention has particular applicability to dynamic random access memory devices.
2. Description of the Background Art
In manufacturing of semiconductor memories, a final test (shipment test) is performed on the memory cells after they are packaged in order to check that the manufactured memory devices will operate correctly. With the final test, it is confirmed that there are no defective memory cells in the memory devices. Briefly, predetermined test data is written into all the memory cells from which the read out data is compared with the written test data. When all the memory cell data read out coincides with the test data, it is concluded that the memory device is normal and may be shipped. However, if a non-coincidence is found in even one memory cell, that memory device is considered to be defective.
Final tests such as those mentioned above are required to be performed on dynamic random access memories (hereinafter referred to as "DRAM") as well as to static random access memories (hereinafter referred to as "SRAM"). However, in the following description, a DRAM will be used as an example.
FIG. 7 is a block diagram of a conventional DRAM 30a. The DRAM 30a of FIG. 7 is shown in U.S. Pat. No. 4,464,750, for example. Referring to FIG. 7, the DRAM 30a comprises a memory array 1 constituted by a number of memory cells, an address buffer 31 for receiving an external address signal ADR, a row decoder 2 and a column decoder 5 responsive to an internal address signal provided from the address buffer 31 for specifying a memory cell in the memory array. A sense amplifier 3 amplifies a data signal from a selected row of memory cells. An input/output buffer 33 receives and provides the data signals via the I/O line to external devices. A control circuit 32 is responsive to externally applied timing signals such as a row address strobe signal RAS, a column address strobe signal CAS, a write control signal W etc. for generating various internal control signals.
A memory tester 35 is connected to the DRAM 30a for executing the final test. The memory tester 35 comprises an address generator 36 for generating an address signal ADR, a test data generator 37 for generating test data D, a comparator 38 for comparing the generated test data D and data Q provided from the DRAM 30, and a control signal generator 39. The control signal generator 39 provides signals RAS, CAS, and W to the DRAM 30.
FIG. 8 is a timing diagram for explaining the test operation of the previously mentioned final test. In the following, the test operation will be described referring to FIGS. 7 and 8.
Firstly, at period 91, a row decoder 2 and a column decoder 5 specify a memory cell in response to an external address signal ADR. At the same time, a predetermined test data Dw is externally supplied to an input buffer 33. The supplied input data D is provided to the specified memory cell through the I/O line into which the data Dw is written. Next, at period 92, the row decoder 2 and the column decoder 5 again specify the same memory cell, from which data Qr is read out. In other words, test data Dw is written into a selected memory cell at period 91 and data Qr is immediately read out during the following period 92. The written data Dw and the read out data Qr are compared with each other to determine whether the specified memory cell is defective or not by checking its coincidence or non-coincidence. Similarly, the writing and reading of the test data are performed on another memory cell at periods 93 and 94.
When the time required to write data into a specified memory cell, i.e. the memory cycle, is Tw, and the time required to read out the data from the specified memory cell is Tr, the total time TT required to carry out the above write/read test for n memory cells is expressed in the following equation, assuming that Tw=Tr: ##EQU1##
There is a problem that the achievement of the final test requires a long period of time when conventional configured circuits are utilized. Particularly, an increase in storage capacity of recent memory devices directly cause an expansion of the test time, as can be appreciated from equation (1).
In order to correctly detect the existence of a defective memory cell, the afore mentioned write/read test must be carried out regarding two test data "0" and "1". This means that two times the time of the total time period TT expressed by equation (2) is necessary.
Referring to FIG. 9, the required testing time will be explained hereinafter presuming that the DRAM comprises 30 memory cells. The DRAM of FIG. 9 comprises a memory array 1 including 30 memory cells of 00-29, a row decoder 2, a sense amplifier 3, an I/O gate circuit 4, a column decoder 5, and a precharge circuit 7. When the time period Tw required for data writing and the time period Tr required for reading are each presumed to be 200n sec (Tw =Tr=200n sec), the total time period TT.sub.1 represented by the following equation is required for the test operation, that is to say, for carrying out writing and reading of test data "0" and "1". ##EQU2##
Regarding a DRAM having 1M (=1,048,576) bits, the total time period TT.sub.2 represented by the following equation is required for carrying out the test operation. ##EQU3##